1. Field of the Invention
The present invention relates to an amplifier circuit.
2. Description of the Related Art
FIG. 9 is a circuit diagram showing a configuration example of a digital power amplifier (see a non-patent document 1). An input signal terminal IN is connected in parallel to a plurality of unit amplifiers 911, 912, . . . via an input impedance matching circuit 901. Each of the unit amplifiers 911, 912, . . . has transistors 902, 903 and an output impedance matching circuit 904. The n-channel field effect transistor 902 has a gate connected to the input signal terminal IN via the input impedance matching circuit 901, and a source connected to a reference potential. The n-channel field effect transistor 903 has a source connected to a drain of the transistor 902, and a drain connected to an output signal terminal OUT via the output impedance matching circuit 904. In the first unit amplifier 911, a gate of the transistor 903 is connected to a switching control signal terminal SW1. In the second unit amplifier 912, a gate of the transistor 903 is connected to a switching control signal terminal SW2.
First, the operation of the first unit amplifier 911 will be described. When the switching control signal terminal SW1 is set to high level, the transistor 903 turns on, and the transistor 902 amplifies an input signal inputted to the input signal terminal IN and outputs the amplified input signal to the output signal terminal OUT. When the switching control signal terminal SW1 is set to low level, the transistor 903 turns off and the transistor 902 does not operate, and therefore no amplified signal is outputted from the output signal terminal OUT.
Next, the operation of the second unit amplifier 912 will be described. When the switching control signal terminal SW2 is set to high level, the transistor 903 turns on and the transistor 902 amplifies the input signal inputted to the input signal terminal IN and outputs the amplified input signal to the output signal terminal OUT. When the switching control signal terminal SW2 is set to low level, the transistor 903 turns off and the transistor 902 does not operate, and therefore no amplified signal is outputted from the output signal terminal OUT.
Control signals of the switching control signal terminals SW1 and SW2 control the operation of the unit amplifiers, whereby an amplification factor of the digital power amplifier can be controlled. Incidentally, since the input signal is a high-frequency RF signal, the impedance matching circuits 901 and 904 are necessary.
To control output power, the digital power amplifier adopts a method depending on the number of the unit amplifiers 911, 912 in operation, instead of depending on input power. A conventional amplifier has a problem that, when an input signal is weak, a ratio of DC bias power for keeping the amplifier in an operating state is high, resulting in low power efficiency. In the digital power amplifier, since the control depends on the number of the unit amplifiers 911, 912 in operation, each of the unit amplifiers operates in a saturated state, and when an input signal is weak, the number of the unit amplifiers 911, 912 in operation is decreased, thereby enabling a reduction in DC bias power. That is, a highly efficient operation is made possible.
[Non-patent document 1] Jin-Han Yoon et al., “A 900 MHz CMOS RF Power Amplifier with Digitally Controllable Output Power”, Proceedings of IEEE TENCON' 02, 2002, pp. 1138-1141
The digital power amplifier in FIG. 9 has the two transistors 902 and 903 connected in cascode, and thus requires a high power supply voltage for driving the two transistors 902 and 903, resulting in an increase in DC bias power, which gives rise to the problem that power efficiency is lowered. Further, since a RF signal is inputted to the transistor 902, the RF signal, though only a little, leaks to the output side. In a case where resolution of the digital power amplifier is increased, this leakage power has an adverse effect.